1. Field of the Invention
This invention relates to memory devices and to field programmable gate arrays programmed by loading a bitstream of data stored in one or more memory devices.
2. Description of the Background Art
"The Programmable Logic Data Book" ("Xilinx Data Book"), published by Xilinx, Inc. ("Xilinx") in 1994, describes field programmable gate arrays ("FPGAs") manufactured and sold by Xilinx. These FPGAs are further described in U.S. Pat. No. Re. 34,363, which is incorporated herein by reference. These FPGAs are capable of retrieving configuration data from a Programmable Read-Only Memory ("PROM") or other memory device. Several methods for retrieving configuration data from a single PROM are described in co-pending application Ser. No. 08/500,294, which is incorporated herein by reference.
Description of Background Art Figures
One method for retrieving a configuration data stream ("bitstream") from a PROM is represented in FIG. 1. This method is referred to as "master serial configuration mode." Referring to FIG. 1, an FPGA 1 receives an initiating signal on reset line 2, which signal also initializes PROM 4. Alternatively, FPGA 1 may self-initialize in response to the application of a supply voltage. FPGA 1 generates a clock signal on a clock signal line 3. The clock signal is received by PROM 4, which generates in response thereto a bitstream DATA on an output line 5. The bitstream DATA is received by FPGA 1, which becomes configured in response thereto. When FPGA 1 is done configuring itself, it asserts an ENABLEB signal on line 6, indicating that configuration is complete. This signal deselects PROM 4.
Known PROMs generate the bitstream DATA on line 5 in FIG. 1 using a structure shown in FIG. 2. Referring to FIG. 2, an address counter 7 is initialized by a signal on reset line 2. Address counter 7 may be either an up counter or a down counter, but does not function as an up/down counter. The address in the counter is sent via address bus 8 to memory block 9. Memory block 9 places the contents of the memory address specified by address bus 8 onto bitstream line 5. Address counter 7 is updated periodically in response to an input clock signal on clock signal line 3, and sends a new address on address bus 8 to memory block 9. In response thereto, memory block 9 places the next bit of bitstream data onto bitstream line 5. When address counter 7 receives an ENABLEB signal on input signal line 6, address counter 7 ceases to count.
A similar method is known for retrieving a bitstream from a parallel PROM.
The term "self-addressing memory device" will be used herein to refer to any storage device that does not require externally supplied addresses to retrieve the data; the term therefore may include, but is not limited to, serial and parallel Programmable Read-Only Memories ("PROMs"), other Read-Only Memories ("ROMs"), and shift registers. These memory devices may be either volatile or non-volatile. The term "self-addressing" as used herein does not imply the necessity for an addressing scheme; for example, shift registers do not require addressing. The term "ROMs" includes both programmable and non-programmable Read-Only Memories, which may provide either serial or parallel data.
No known self-addressing memory has the capability of setting the initial value in the counter to any of two or more values. No known self-addressing memory has the capability of optionally both incrementing and decrementing the internal counter.
In co-pending application Ser. No. 08/500,294, Leeds also describes a configuration method wherein the system includes first and second FPGAs, as shown in FIG. 3. The FIG. 3 system includes first and second FPGAs 1a and 1b and PROM 4. During configuration, FPGA 1a is in the "master serial configuration mode" and FPGA 1b is in the "slave serial configuration mode." (These configuration modes are described in the Xilinx Data Book on pages 2-32 to 2-35.) FPGA 1a, the master device, provides the signals that control the configuration of both master and slave devices. In response to an initiating signal on reset line 2, which also initializes FPGA 1b and PROM 4, or in response to the application of a supply voltage, FPGA 1a generates a clock signal on a clock signal line 3. This clock signal is input to both PROM 4 and FPGA 1b. PROM 4 responds to the clock signal by providing bitstream data signals to FPGA 1a on line 5. In this example, when FPGA 1a is done configuring itself, FPGA 1a continues to send clock signals to serial PROM 4 and FPGA 1b on signal line 3. Serial PROM 4 thus continues to send bitstream data to FPGA 1a via line 5. This data is passed from FPGA 1a to FPGA 1b via a signal line 10. FPGA 1b takes the bitstream data from line 10 and uses that data to configure itself. FPGAs 1a and 1b include open drain output buffers which drive leads 6a and 6b, respectively. Leads 6a and 6b are "wire-ANDed" together. That is, each of leads 6a and 6b is an open-drain output lead. They are tied to each other and also tied through a resistor 31 to a positive power supply 32. When FPGAs 1a and 1b are both done being configured, the signals on leads 6a and 6b go high, indicating that both FPGAs are done being configured. The high signals on leads 6a and 6b produce a high signal (ENABLEB) which deselects PROM 4.
It is known that the configuration method shown in FIG. 3 can be extended to permit configuration of more than two FPGAs with a single bitstream.
A similar method is known to retrieve a bitstream from a parallel PROM and configure multiple FPGAs. The parallel bitstream data is serialized by the master device, corresponding to FPGA 1a in FIG. 3. When FPGA 1a is done configuring itself, it sends the serialized bitstream to FPGA 1b via a signal line corresponding to signal line 10 in FIG. 3.
It is also known to use multiple PROMs to store a bitstream too large to fit in a single PROM of the size used in a given system. This technique is called "cascading." One example is shown on page 2-32 of the 1994 Xilinx Data Book. This example shows an FPGA in "master serial configuration mode" with first and second cascaded serial PROMs forming a "cascade chain." This method is shown in FIG. 4. Referring to FIG. 4, an FPGA 1 in master serial configuration mode receives an initiating signal on reset line 2, which also initializes PROMs 4a and 4b. Alternatively, FPGA 1 may self-initialize in response to the application of a supply voltage. FPGA 1 generates a clock signal on a clock signal line 3. The clock signal is received by serial PROMs 4a and 4b. PROM 4a generates in response thereto a bitstream on an output line 5. PROM 4b does not generate a bitstream at this time, because PROM 4a also generates a chip enable signal on output line 11, which disables PROM 4b until all of the contents of PROM 4a have been placed on bitstream signal line 5. When all of the contents of PROM 4a have been read, PROM 4a ceases to place data on bitstream signal line 5 and changes the state of chip enable signal 11. Thus PROM 4b begins to generate bitstream data on line 5. The serial data on line 5 is received by FPGA 1, which becomes configured in response thereto. When FPGA 1 is done configuring itself, it asserts an ENABLEB signal on line 6, indicating that configuration is complete. This signal deselects PROM 4a. In response thereto, PROM 4b changes the state of chip enable signal 11, which deselects PROM 4b.
A similar method is known to retrieve a bitstream from multiple parallel PROMS.
Disadvantages of the Background Art
One advantage of using FPGAs in a system is the capability of reconfiguring the FPGA or FPGAs to perform a different function without making physical changes to the system. It can be desirable to store multiple bitstreams in a PROM (or in a series of PROMs as in FIG. 4) to permit such reconfiguration. The known method for storing multiple bitstreams is to store the bitstream data sequentially in the PROM, such that after the FPGA or FPGAs are completely configured, the internal counter in the PROM addresses the first location in the next bitstream. The data at this address is then available if another configuration is initiated.
A disadvantage of this method is that the bitstreams can only be accessed in the same sequential order as they are stored in the PROM. Initializing the PROM counter permits access to the first bitstream at any time, but any further bitstreams can only be accessed sequentially.
Another method for storing multiple bitstreams in a single PROM is to segment the PROM into two or more banks of memory locations ("memory banks"), and to select one of the memory banks based on one or more "bank select" input signal lines to the PROM. This method overcomes the disadvantage of sequential access, but the size of a bitstream is limited to the size of one memory bank of the PROM. As an additional disadvantage, this method is unsuited to the storage of bitstreams of widely varying sizes. Such bitstreams are required in multiple-FPGA systems where it is sometimes desired to configure several FPGAs, and sometimes to configure only one or a few FPGAs. The size of each memory bank must be such that the largest bitstream can be stored in a single memory bank. This structure and method result in wasted memory storage in the memory banks containing the smaller bitstreams.
It is desirable to create a self-addressing memory device which can efficiently store multiple bitstreams of varying sizes, while allowing access to any bitstream at any time.